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Selected Refereed Papers: (for complete list please
check my CV ) [1] Arun K. Kanuparthi, Mohamed Zahran, and Ramesh Karri, Architecture Support for Dynamic Integrity Checking, IEEE Transactions on Information Forensics and Security (to appear). [2] Corey Malone, Mohamed Zahran, and Ramesh Karri, Are Hardware Performance Counters a Cost Effective Way for Integrity Checking of Programs?, The Sixth ACM Workshop on Scalable Trusted Computing, October 2011. (pdf) [3] Mohamed Salah Souahi, Smail Niar, Mohamed Zahran, Mohamed Benmohamed, Towards Dynamic Cache Block Placement for Multi-processor NUCA, IEEE International Conference on Microelectronics, December 2011. [4] Artem Durytskyy, Mohamed Zahran, and Ramesh Karri, Improving Robustness of GPUs by Making Use of Faulty Parts, Proc. International Conference on Computer Design (ICCD11), October 2011. (pdf) [5] Arun K. Kanuparthi, Mohamed Zahran, and Ramesh Karri, Feasibility Study of Dynamic Trusted Platform Module, Proc. International Conference on Computer Design (ICCD10), [6] Ahmed Youssef, Mohamed Zahran, Mohab Anis, and Mohamed Elmasry,
On the Power Management of Simultaneous
Multithreading Processors, IEEE Transactions on VLSI , [7] Mohamed Zahran and Sally A. McKee, Global Management of Cache Hierarchies , The ACM International Conference on Computing Frontiers (CF'10), Italy, May 2010. (pdf) [8] Yufu Zhang , Ankur Srivastava and Mohamed Zahran, On-Chip Sensor Driven Efficient Thermal Profile Estimation Algorithms, ACM Transactions on Design Automation of Electronic Systems, Vol 15, issue 3, May 2010.[9] Kim Hazelwood and Mohamed Zahran. Challenges and Opportunities at All Levels: Interactions Among Operating Systems, Compilers, and Multicore Processors, ACM SIGOPS Operating System Review. Volume 43, Issue 2. April 2009.[10] Najla Alfaraj,
H. Jonathan Chao, and Mohamed Zahran, NBC: Network-based
Cache Coherence Protocol for Multistage NoCs, in The International SoC Design Conference
(ISOCC), 2009.
[11] Bushra Ahsan and Mohamed Zahran, Managing
Off-Chip Bandwidth: A Case for Bandwidth-Friendly Replacement Policy, in The 2nd
Workshop on Managed Multi-Core Systems (MMCS'09), held in
conjunction
with ASPLOS 2009. (pdf)
[12]
Mohamed Zahran and Sally A. McKee, Adaptive Block Placement
Policy for Cache Hierarchies,in SMART'09:3rd Workshop on Statistical
and Machine learning approaches to ARchitectures and compilaTion, held
in conjunction with HiPEAC 2009. (pdf) [13] Bushra
Ahsan and Mohamed Zahran, Cache Performance, System Performance,
and Off-Chip Bandwidth... Pick any Two
, in 3rd workshop Interconnection Network
Architectures: On-Chip, Multi-Chip (INA-OCMC), held in
conjunction with HiPEAC 2009. (pdf)
[17] Mohamed
Zahran, Kursad Albayraktaroglu, and Manoj Franklin,
Non-Inclusion Property in multi-level Caches Revisited, in the International
Journal of Computers and Their Applications Special Issue on
Techniques and Architectures for High Performance and Energy
Efficient Computing Systems, Vol 14, Num 2, June 2007. ( bib,
pdf) [19] Mohamed
Zahran and Anasua Bhowmik, Bandwidth-Friendly Cache Hierarchy, in The 2006 International Conference on Computer
Design (CDES06), Las Vegas, 2006. (bib, pdf) [20] Mohamed
Zahran and Anasua Bhowmik, Hybrid Compiler and Microarchitecture Technique for Cache Traffic Optimization, in
9th Workshop on Interaction between Compilers and Computer
Architectures (INTERACT 9), held in Conjunction with the 11th
International Symposium
on High-Performance Computer Architecture (HPCA-11), 2005. (bib, pdf) [21] Francois Cantonnet, Yiyi Yao, Mohamed Zahran and Tarek El-Ghazawi, Productivity Analysis of the UPC Language, in 3rd International Workshop on Performance Modeling, Evaluation, and Optimization of Parallel and Distributed Systems (PMEO-PDS), to be held in conjunction with the International Parallel and Distributed Processing Symposium (IPDPS 2004). [22] Mohamed
Zahran and Manoj Franklin, Dynamic Thread Resizing for Speculative Multithreaded
Processors, in International Conference
on Computer
Design (ICCD), San Jose, CA, October, 2003. (ps)(pdf) (Best Paper Award)
[23] Mohamed
Zahran, Manoj Franklin and Renju Thomas, Confidence Estimation
for Register Value
Communication in Speculative Multithreaded
Architectures, in first value prediction workshop
(VPW1), held in conjunction with the 30th
Annual International Symposium on Computer
Architecture (ISCA), San Diego, California, 2003. (ps)(pdf) [24] Mohamed
Zahran, On Cache Memory Hierarchy for Chip-Multiprocessor, in MEDEA workshop held in conjunction
with PACT 2002 Conference, Charlottesville, Virginia, 2002. Also
Appeared in ACM Computer Architecture News, Vol 31, No. 1,
March 2003. [25] Mohamed
Zahran and Manoj Franklin, Return Address Prediction in
Speculative Multithreaded Environments, in Int'l Conference on
Hi-Performance Computing, Bangalore, India, 2002. (ps)(pdf) [26] Mohamed
Zahran and Manoj Franklin, A Feasibility Study of Hierarchical
Multithreading, in International
Parallel and Distributed Processing Symposium (IPDPS 2002),
Marriott Marina, Fort Lauderdale, Florida, 2002. (ps)
(pdf) [27] Mohamed
Zahran and Manoj Franklin, Hierarchical Multi-threading
For Exploiting Parallelism
at Multiple Granularities, Workshop on
MULTITHREADED EXECUTION, ARCHITECTURE and COMPILATION (MTEAC-5), Austin, Texas, 2001. (ps)
(pdf) [28]
Mohamed Zahran, Ashraf Abdel-Wahab and Samir Shaheen, Adaptive
Genetic Algorithm
for Multiprocessor Scheduling, poster
presentation at the Genetic and Evolutionary Computation Conference (GECCO),
Orlando, 1999. Selected Presentations & Talks (for complete list
please check my CV
): [1] "Off-Chip
Bandwidth: The New Wall in The Multicore Era", in CS
Departmental seminar series, University of Delaware. [2] "Cache
Replacement Policy Revisited", in The Annual Workshop on
Duplicating, Deconstructing, and [4]"RHT:
A Context-Based Return Address Predictor", at CDES 2006. [5] "Bandwidth-Friendly
Cache Hierarchy", at CDES 2006. [6]
"Chip Multithreading: Issues and Challenges", in the ECE
departmental seminar, University of Massachusetts Amherst (pdf). [7]
"Hybrid Compiler and Microarchitecture Technique for Cache Traffic
Optimization", in 9th Workshop on Interaction between [8]
" Confidence Estimation for Register Value Communication in
Speculative Multithreaded Architectures", [9]
"Speculative Multithreading...The Future of Microprocessors",
[10]
"Microprocessors...Can We Make Further Progress", [11]
"On Cache Memory Hierarchy for Chip-Multiprocessor", in
MEDEA workshop, [12]
"Feasibility Study of Hierarchical Multithreading", in IPDPS
Conference, Florida, 2002. |