Home Page of Mohamed M. Zahran

My research interest is in Computer Architecture in general. Currently my research work targets multicore and manycore architectures and how to make them faster, trusted, and power-efficient.

How can the hardware assist in ensuring that the running program is not tampered and only legitimate software is allowed to execute?

Memory System Hierarchy Design
CHESS (Cache Hierarchy Extremely Scalable and Smart)

The ever increasing performance gap between the processor and memory, as well as the widespread usage of multi-core chips,
require a totally new way of building memory hierarchy. In this project, we study different ways of making cache hierarchy
more efficient in terms of hit/miss rates, access time, bandwidth requirements (both on-chip and off-chip), scalability, and power.
Basically, we try to answer the following questions:

How does the cache hierarchy look like for 100 on-chip cores?
What do we do with the bandwidth wall, both off-chip and on-chip?
What is the effect of 3D stacking on bandwidth wall ?

We are developing a state of the art run time power management strategy
for optimizing the leakage power as well as dynamic power in high performance
pipelines through effective body biasing, shutdown and supply voltage scaling.
This strategy would include a range of optimization techniques working in a synergistic fashion.