Project Description

With the tremendous enhancements done in process technology, having chip multiprocessor is nowadays the main architecture in use, as evidenced by the wide usage of Intel Core-duo (2 processors on chip). Also there are high end processors, such as SUN Ultrasparc Niagara that has 8 processors on chip. The number of cores per-chip is expected to double almost every two years. However, we cannot get the best performance from these cores, unless we have an efficient memory system, which is the main topic of this project.

Memory is around 1000 times slower than the processor. Therefore, almost all the current processors have several caches organized as cache hierarchy, which are small, fast and expensive memory modules, on-chip with the processors. With many on-chip processors, the design of this cache hierarchy becomes more challenging.

There are several hard questions to answer, for instance, will each core have its own cache or will they all share the cache? If the number of cores increases beyond 4 or 8, they cannot all share a cache. But if these cores need to communicate together, they usually communicate through cache. The main question that this project tries to answer is: how will the cache hierarchy look like when the number of on-chip cores increases beyond 16 processors? 

To do that we use a simulator that simulates chip-multiprocessor. The project will involve many simulations, coding to modify the simulations, data analysis and, of course, brainstorming.